Microprocessor Which of the following interrupt is both level and edge sensitive? RST 7.5 TRAP INTR RST 5.5 RST 7.5 TRAP INTR RST 5.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In an intel 8085A, which is the first machine cycle of an instruction? A memory read cycle A memory write cycle An I/O read cycle An op-code fetch cycle A memory read cycle A memory write cycle An I/O read cycle An op-code fetch cycle ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Segment override prefix (SOP) is used when a default offset register is not used with its default base segment register but with a different base register. Reason(R): The offset registers IP and SP can never be associated with any other segment registers apart from their respective default segments. A is true but R is false. A is false but R is true. Both A & R are true and R is the correct explanation of A. Both A & R are true but R is not the correct explanation of A. A is true but R is false. A is false but R is true. Both A & R are true and R is the correct explanation of A. Both A & R are true but R is not the correct explanation of A. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A bus connected between the CPU and main memory that permits transfer of information between main memory and the CPU is known as Memory bus DMA bus Control bus Address bus Memory bus DMA bus Control bus Address bus ANSWER DOWNLOAD EXAMIANS APP
Microprocessor When the write enable input is not asserted, the gated D latch _________ its output. Clears Complements Can not change Sets Clears Complements Can not change Sets ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The five flags in 8085 are designated as Z, CY, S, P and AC Z, CY, S, D, AC Z, C, S, P, AC D, Z, S, P, AC Z, CY, S, P and AC Z, CY, S, D, AC Z, C, S, P, AC D, Z, S, P, AC ANSWER DOWNLOAD EXAMIANS APP
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