Microprocessor Which of the following interrupt is both level and edge sensitive? INTR TRAP RST 7.5 RST 5.5 INTR TRAP RST 7.5 RST 5.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion (A): Negative values of incremental operator in DO loop are allowed in Fortran 77 but not in earlier versions of Fortran. Reason (R): Fortran 77 has better array facilities than earlier versions of Fortran. A is correct R is wrong Both A and R are correct but R is not correct explanation of A Both A and R are correct and R is correct explanation of A A is wrong R is correct A is correct R is wrong Both A and R are correct but R is not correct explanation of A Both A and R are correct and R is correct explanation of A A is wrong R is correct ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The content of the A15-A8 (higher order address lines) while executing “IN 8-bit port address” instruction are all bits set (i.e. FFH) all bits reset (i.e. 00H) irrelevant same as the content of A7-A0 all bits set (i.e. FFH) all bits reset (i.e. 00H) irrelevant same as the content of A7-A0 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The cycle required to fetch and execute an instruction in a 8085 microprocessor is which one of the following? Memory cycle Instruction cycle Machine cycle Clock cycle Memory cycle Instruction cycle Machine cycle Clock cycle ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During the execution of the instruction, the ________tests the status and control flags and updates them based on the results of executing the instruction. Bus Interface Unit (BIU) None of these Both ‘c’ and ‘d’ Execution Unit (EU) Bus Interface Unit (BIU) None of these Both ‘c’ and ‘d’ Execution Unit (EU) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Consider the following I) Sign flag II) Trap flag III) Parity flag IV) Auxiliary carry flag. Which one of the above flags is/are present in 8085 microprocessor? (I) only (I) ,(III) & (IV) (I) & (II) (II) & (III) (I) only (I) ,(III) & (IV) (I) & (II) (II) & (III) ANSWER DOWNLOAD EXAMIANS APP
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