Microprocessor When the write enable input is not asserted, the gated D latch _________ its output. Complements Can not change Sets Clears Complements Can not change Sets Clears ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Consider the following I) Sign flag II) Trap flag III) Parity flag IV) Auxiliary carry flag. Which one of the above flags is/are present in 8085 microprocessor? (I) & (II) (II) & (III) (I) ,(III) & (IV) (I) only (I) & (II) (II) & (III) (I) ,(III) & (IV) (I) only ANSWER DOWNLOAD EXAMIANS APP
Microprocessor After RESET 8255 will be in mode 0; all ports are input unchanged condition mode 2 mode 0; all ports are output mode 0; all ports are input unchanged condition mode 2 mode 0; all ports are output ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 microprocessor system with memory mapped I/O, which of the following is true? Devices are accessed using IN and OUT instructions Arithmetic and logic operations can be directly performed with the I/O data Devices have 8-bit address line There can be maximum of 256 input devices and 256 output devices Devices are accessed using IN and OUT instructions Arithmetic and logic operations can be directly performed with the I/O data Devices have 8-bit address line There can be maximum of 256 input devices and 256 output devices ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The address bus width of a microprocessor which is capable of addressing 64 Kbytes of the memory is 12 16 20 8 12 16 20 8 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assuming LSB is at position 0 and MSB at position 7, which bit positions are not used (Undefined) in flag register of an 8085 microprocessor? 1, 3, 4 2, 3, 5 1, 3, 5 1, 2, 5 1, 3, 4 2, 3, 5 1, 3, 5 1, 2, 5 ANSWER DOWNLOAD EXAMIANS APP
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