Microprocessor
The microprocessor issues ALE during first T-state of

 fetch cycle only
 every machine cycle
 memory READ cycle only
 memory WRITE cycle only

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Microprocessor
The output data lines of microprocessor and memories are usually tristated because

 More than one device can transmit over the data bus at the same time
 More than one device can transmit information over the data bus by enabling only one device at a time
 It increases the speed of data transfer over the data bus
 The data line can be multiplexed for both input and output

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Microprocessor
PUSH B instruction in 8085 microprocessor causes

 registers B & C to be cleared
 the contents of register B only to be copied in the stack
 the contents of registers B & C to be transferred in the stack and and the registers get cleared
 the contents of register B & C to be copied in the stack

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