Microprocessor
The length of bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an indeterminate number of wait state clock cycles denoted by Tw. The wait states are always inserted between

 T4 & T1
 T1 & T2
 T3 & T4
 T2 & T3

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Microprocessor
Which of the following is not true during the execution of an interrupt service routine, which does not contain any EI instructions

 the microprocessor cannot be interrupted by any mask able interrupt
 all interrupts except non-maskable interrupt are disabled
 the microprocessor cannot be interrupted by any interrupt
 the microprocessor can be interrupted by a non-mask able interrupt

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