Microprocessor After RESET 8255 will be in mode 0; all ports are input mode 2 mode 0; all ports are output unchanged condition mode 0; all ports are input mode 2 mode 0; all ports are output unchanged condition ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A sequence of two registers that multiplies the content of DE register pair by two and stores the result in HL register pair (in 8085 assembly language) is XCHG & DAD B XTHL & DAD H PCHL & DAD D XCHG & DAD H XCHG & DAD B XTHL & DAD H PCHL & DAD D XCHG & DAD H ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Inintel 8085A microprocessor ALE signal is made high to Enable the data bus to be used as low order address bus To disable data bus To latch data D0-D7 from data bus To achieve all the functions listed above Enable the data bus to be used as low order address bus To disable data bus To latch data D0-D7 from data bus To achieve all the functions listed above ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. Bus Interface Unit (BIU) None of these Execution Unit (EU) Both ‘b’ and ‘c’ Bus Interface Unit (BIU) None of these Execution Unit (EU) Both ‘b’ and ‘c’ ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Output of the assembler in machine codes is referred to as Source program Object program Macroinstruction Symbolic addressing Source program Object program Macroinstruction Symbolic addressing ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A combinational PLD with a programmable AND array and a programmable OR array is called a PAL PROM PLA PLD PAL PROM PLA PLD ANSWER DOWNLOAD EXAMIANS APP
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