Microprocessor After RESET 8255 will be in mode 2 mode 0; all ports are input mode 0; all ports are output unchanged condition mode 2 mode 0; all ports are input mode 0; all ports are output unchanged condition ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Register pair used to indicate memory B and C W and Z H and L D and E B and C W and Z H and L D and E ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The stack is nothing but a set of reserved ROM address space None of these reserved I/O address space reserved RAM address space reserved ROM address space None of these reserved I/O address space reserved RAM address space ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? T3 OP code fetch T2 OP code fetch T4 OP code fetch T1 OP code fetch T3 OP code fetch T2 OP code fetch T4 OP code fetch T1 OP code fetch ANSWER DOWNLOAD EXAMIANS APP
Microprocessor At the beginning of a fetch cycle, the contents of the program counter are transferred to address bus. transferred to memory data register. transferred to memory address register . incremented by one. transferred to address bus. transferred to memory data register. transferred to memory address register . incremented by one. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor DS directive in 8085 None of these Forces the assembler to reserve a specified number of bytes in the memory Forces the assembler to reserve one byte of memory Forces the assembler to reserve a specified number of consecutive bytes in the memory None of these Forces the assembler to reserve a specified number of bytes in the memory Forces the assembler to reserve one byte of memory Forces the assembler to reserve a specified number of consecutive bytes in the memory ANSWER DOWNLOAD EXAMIANS APP
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