Microprocessor During OPCODE fetch the state of S0 and S1 is 00 10 11 01 00 10 11 01 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which general register or general register pair is incremented/decremented by 2 during PUSH and POP instructions? Stack Pointer. D-E. Program Counter. H-L. Stack Pointer. D-E. Program Counter. H-L. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A microprocessor differentiates between op code, data/address at any time by the sequence in which memory contents are fetched by it the stack pointer its internal registers the program counter the sequence in which memory contents are fetched by it the stack pointer its internal registers the program counter ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Address bus is unidirectional. Reason(R): Data bus is bidirectional Both A & R are true and R is the correct explanation of A A is true but R is false A is false but R is true Both A & R are true but R is not the correct explanation of A Both A & R are true and R is the correct explanation of A A is true but R is false A is false but R is true Both A & R are true but R is not the correct explanation of A ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? T3 OP code fetch T2 OP code fetch T1 OP code fetch T4 OP code fetch T3 OP code fetch T2 OP code fetch T1 OP code fetch T4 OP code fetch ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The stack is nothing but a set of reserved ROM address space None of these reserved I/O address space reserved RAM address space reserved ROM address space None of these reserved I/O address space reserved RAM address space ANSWER DOWNLOAD EXAMIANS APP
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