Microprocessor During OPCODE fetch the state of S0 and S1 is 10 00 11 01 10 00 11 01 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A mask programmed ROM is erasable and programmable erasable electrically programmed by the user programmed at the time of fabrication erasable and programmable erasable electrically programmed by the user programmed at the time of fabrication ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In an intel 8085A, which is the first machine cycle of an instruction? An I/O read cycle An op-code fetch cycle A memory write cycle A memory read cycle An I/O read cycle An op-code fetch cycle A memory write cycle A memory read cycle ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assuming LSB is at position 0 and MSB at position 7, which bit positions are not used (Undefined) in flag register of an 8085 microprocessor? 1, 2, 5 2, 3, 5 1, 3, 4 1, 3, 5 1, 2, 5 2, 3, 5 1, 3, 4 1, 3, 5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 name/names of the 16 bit registers is/are both A and B. none of these. stack pointer. program counter. both A and B. none of these. stack pointer. program counter. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Ready signal of microprocessor is used to detect whether a peripheral is ready for the data transfer or not. Reason(R): In the microprocessor during data transfer operations, the wait states are added by forcing the ready signal low. A is true but R is false. Both A & R are true and R is the correct explanation of A. Both A & R are true but R is not the correct explanation of A . A is false but R is true. A is true but R is false. Both A & R are true and R is the correct explanation of A. Both A & R are true but R is not the correct explanation of A . A is false but R is true. ANSWER DOWNLOAD EXAMIANS APP
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