Microprocessor In a vector interrupt none. the branch address is obtained from a register in the processor. the interrupting source supplies the branch information to the processor through an interrupt vector. the branch address is assigned to a fixed location in memory. none. the branch address is obtained from a register in the processor. the interrupting source supplies the branch information to the processor through an interrupt vector. the branch address is assigned to a fixed location in memory. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A bus connected between the CPU and main memory that permits transfer of information between main memory and the CPU is known as Address bus Memory bus Control bus DMA bus Address bus Memory bus Control bus DMA bus ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following pair of gates can form a latch? A pair of cross coupled NAND A cross coupled NAND/OR A pair of cross copled AND A pair of cross coupled OR A pair of cross coupled NAND A cross coupled NAND/OR A pair of cross copled AND A pair of cross coupled OR ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Consider the following I) Sign flag II) Trap flag III) Parity flag IV) Auxiliary carry flag. Which one of the above flags is/are present in 8085 microprocessor? (I) only (II) & (III) (I) ,(III) & (IV) (I) & (II) (I) only (II) & (III) (I) ,(III) & (IV) (I) & (II) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 microprocessor based system maximum possible number of input/output devices can be connected using I/O mapped I/O technique is 65536 512 64 256 65536 512 64 256 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor When the write enable input is not asserted, the gated D latch _________ its output. Can not change Sets Complements Clears Can not change Sets Complements Clears ANSWER DOWNLOAD EXAMIANS APP
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