Microprocessor The output data lines of microprocessor and memories are usually tristated because The data line can be multiplexed for both input and output It increases the speed of data transfer over the data bus More than one device can transmit information over the data bus by enabling only one device at a time More than one device can transmit over the data bus at the same time The data line can be multiplexed for both input and output It increases the speed of data transfer over the data bus More than one device can transmit information over the data bus by enabling only one device at a time More than one device can transmit over the data bus at the same time ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion (A): Negative values of incremental operator in DO loop are allowed in Fortran 77 but not in earlier versions of Fortran. Reason (R): Fortran 77 has better array facilities than earlier versions of Fortran. Both A and R are correct but R is not correct explanation of A A is wrong R is correct A is correct R is wrong Both A and R are correct and R is correct explanation of A Both A and R are correct but R is not correct explanation of A A is wrong R is correct A is correct R is wrong Both A and R are correct and R is correct explanation of A ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In an intel 8085A, which is the first machine cycle of an instruction? An I/O read cycle A memory write cycle An op-code fetch cycle A memory read cycle An I/O read cycle A memory write cycle An op-code fetch cycle A memory read cycle ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the data transfer is not possible in microprocessor memory to accumulator memory to memory accumulator to memory I/O device to accumulator memory to accumulator memory to memory accumulator to memory I/O device to accumulator ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following instruction will never affect the zero flag? ORA R DCR R DCX Rp XRA R ORA R DCR R DCX Rp XRA R ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following conditions is not allowed in an RS latch? R is negated, S is negated R is asserted, S is asserted R is negated, S is asserted R is asserted, S is negated R is negated, S is negated R is asserted, S is asserted R is negated, S is asserted R is asserted, S is negated ANSWER DOWNLOAD EXAMIANS APP
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