Microprocessor Assertion(A): Segment override prefix (SOP) is used when a default offset register is not used with its default base segment register but with a different base register. Reason(R): The offset registers IP and SP can never be associated with any other segment registers apart from their respective default segments. Both A & R are true and R is the correct explanation of A. A is true but R is false. A is false but R is true. Both A & R are true but R is not the correct explanation of A. Both A & R are true and R is the correct explanation of A. A is true but R is false. A is false but R is true. Both A & R are true but R is not the correct explanation of A. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Ready signal of microprocessor is used to detect whether a peripheral is ready for the data transfer or not. Reason(R): In the microprocessor during data transfer operations, the wait states are added by forcing the ready signal low. Both A & R are true but R is not the correct explanation of A . A is false but R is true. A is true but R is false. Both A & R are true and R is the correct explanation of A. Both A & R are true but R is not the correct explanation of A . A is false but R is true. A is true but R is false. Both A & R are true and R is the correct explanation of A. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Program counter in a digital computer Points the memory address of the next instruction to be fetched. Counts the numbers of programs run in the machine. Counts the number of times a subroutine is called. Counts the number of times the loops are executed. Points the memory address of the next instruction to be fetched. Counts the numbers of programs run in the machine. Counts the number of times a subroutine is called. Counts the number of times the loops are executed. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? T3 OP code fetch T2 OP code fetch T4 OP code fetch T1 OP code fetch T3 OP code fetch T2 OP code fetch T4 OP code fetch T1 OP code fetch ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assuming LSB is at position 0 and MSB at position 7, which bit positions are not used (Undefined) in flag register of an 8085 microprocessor? 2, 3, 5 1, 2, 5 1, 3, 4 1, 3, 5 2, 3, 5 1, 2, 5 1, 3, 4 1, 3, 5 ANSWER DOWNLOAD EXAMIANS APP
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