Digital Electronics In an SR latch built from NOR gates, which condition is not allowed S=1, R=0 S=0, R=0 S=0, R=1 S=1, R=1 S=1, R=0 S=0, R=0 S=0, R=1 S=1, R=1 ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics Temperature variation is a/an Digital quantity None Analog quantity Either Digital or Analog quantity Digital quantity None Analog quantity Either Digital or Analog quantity ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics "What would happen, if smaller logic modules are utilized for performing logical functions associated with FPGA? A. Propagation delay will increase B. FPGA area will increase C. Wastage of logic modules will not be prevented D. Number of interconnected paths in device will decrease" B & C A & D A & B C & D B & C A & D A & B C & D ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics When will be the output of an OR gate is LOW ? When any input is LOW When any input is HIGH When all input is LOW When all inputs are HIGH When any input is LOW When any input is HIGH When all input is LOW When all inputs are HIGH ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics An AND gate can be imagined as transistors connected in paralle transistors connected in series switches connected in series switches connected in parallel transistors connected in paralle transistors connected in series switches connected in series switches connected in parallel ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics In VLSI, the number of gate circuits per chip is 50,000 to 99,999 < 10,000 10,000 to 99,999 > 10,000 50,000 to 99,999 < 10,000 10,000 to 99,999 > 10,000 ANSWER DOWNLOAD EXAMIANS APP
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