Microprocessor ‘Burst refresh’ in DRAM is also called None of these Distributed refresh Concentrated refresh Hidden refresh None of these Distributed refresh Concentrated refresh Hidden refresh ANSWER DOWNLOAD EXAMIANS APP
Microprocessor S0 and S1 pins are used for None of these serial communication acknowledging the interrupt indicating the processor’s status None of these serial communication acknowledging the interrupt indicating the processor’s status ANSWER DOWNLOAD EXAMIANS APP
Microprocessor What is SIM? Set interrupt mask. Sorting interrupt mask. None of these. Select interrupt mask. Set interrupt mask. Sorting interrupt mask. None of these. Select interrupt mask. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Of the following circuits, the one which involves storage is Nand Mux RS Latch Decoder Nand Mux RS Latch Decoder ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The content of the A15-A8 (higher order address lines) while executing “IN 8-bit port address” instruction are all bits set (i.e. FFH) all bits reset (i.e. 00H) same as the content of A7-A0 irrelevant all bits set (i.e. FFH) all bits reset (i.e. 00H) same as the content of A7-A0 irrelevant ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Consider the following I) Sign flag II) Trap flag III) Parity flag IV) Auxiliary carry flag. Which one of the above flags is/are present in 8085 microprocessor? (II) & (III) (I) ,(III) & (IV) (I) only (I) & (II) (II) & (III) (I) ,(III) & (IV) (I) only (I) & (II) ANSWER DOWNLOAD EXAMIANS APP
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