Microprocessor A single instruction to clear the lower nibble of accumulator in 8085 language assembly is XRI FOH ANI OFH ANI F0H XRI 0FH XRI FOH ANI OFH ANI F0H XRI 0FH ANSWER DOWNLOAD EXAMIANS APP
Microprocessor SPHL instruction copies the content of H-L register pair to the _________. Stack Pointer D-E B-C PSW Stack Pointer D-E B-C PSW ANSWER DOWNLOAD EXAMIANS APP
Microprocessor At the beginning of a fetch cycle, the contents of the program counter are transferred to memory address register . transferred to address bus. transferred to memory data register. incremented by one. transferred to memory address register . transferred to address bus. transferred to memory data register. incremented by one. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A combinational PLD with a fixed AND array and a programmable OR array is called a PLD PAL PROM PLA PLD PAL PROM PLA ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which one of the following is not correct? Bus is a group of wires Bootstrap is a technique or device for loading first instruction An interrupt signal is required at the start of every program An instruction is a set of bits that defines a computer operation Bus is a group of wires Bootstrap is a technique or device for loading first instruction An interrupt signal is required at the start of every program An instruction is a set of bits that defines a computer operation ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The output data lines of microprocessor and memories are usually tristated because More than one device can transmit over the data bus at the same time The data line can be multiplexed for both input and output More than one device can transmit information over the data bus by enabling only one device at a time It increases the speed of data transfer over the data bus More than one device can transmit over the data bus at the same time The data line can be multiplexed for both input and output More than one device can transmit information over the data bus by enabling only one device at a time It increases the speed of data transfer over the data bus ANSWER DOWNLOAD EXAMIANS APP
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