Digital Electronics A gate is disabled when its disable input is at logic 0. The gate is NOR none of these OR AND NOR none of these OR AND ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics In LSI, the number of gate circuits per chip is < 10,000 100 to 999 1000 to 10,000 100 to 9,999 < 10,000 100 to 999 1000 to 10,000 100 to 9,999 ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics In VLSI, the number of gate circuits per chip is > 10,000 50,000 to 99,999 < 10,000 10,000 to 99,999 > 10,000 50,000 to 99,999 < 10,000 10,000 to 99,999 ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics Why small bubble is given on the output of the NAND gate symbol ? Open collector output None of these Tristate Output is inverted Open collector output None of these Tristate Output is inverted ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics What will be Excess - 3 code for decimal ( 584 )? (0111 0100 1000). (1000 1011 0111). (1011 0111 1000). (1000 0111 1110). (0111 0100 1000). (1000 1011 0111). (1011 0111 1000). (1000 0111 1110). ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics When will be the output of an exclusive-OR gate is HIGH ? The inputs are equal All inputs are LOW All inputs are HIGH The inputs are different The inputs are equal All inputs are LOW All inputs are HIGH The inputs are different ANSWER DOWNLOAD EXAMIANS APP
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